TestDrive Profiling Master
· C / C++ / VERILOG design support.
· CI(Continuous Integration) testing environment
· Fully FPGA virtual simulation & Supports real FPGA driving
· All free to use, opensource project
TestDrive Profiling Master is a free simulation software for Verilog/SystemVerilog and C/C++.
It supports a CI (Continuous Integration) activity for H/W & S/W engineers' close cooperation.
Run by MS Windows environment, its use is governed by The 3-Clause BSD License.
Based on the powerful compiler Verilator and GCC/CLANG, TestDrive Profiling Master provides a totally free virtual FPGA system environment with various dynamic documents for profiling in deep on your system design. It performs a seamless conversion to a real FPGA environment without any changes of your testing software.
I hope you will accomplish a successful design with TestDrive Profiling Master.
Refer to Wiki page for more details.
Language support : الْعَرَبيّة, 中文简体, 中文繁體, Deutsch, English, Español, 日本語, 한국어, Русский
